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Physical Dimensions
8
5.00
4.80
3.81
5
A
B
0.65
6.20
5.80
PIN ONE
1
4
4.00
3.80
1.75
5.60
INDICATOR
(0.33)
1.27
0.25
C B A
1.27
LAND PATTERN RECOMMENDATION
0.25
SEE DETAIL A
0.10
0.25
1.75 MAX
R0.10
R0.10
8°
0°
0.90
0.40
C
0.51
0.33
0.50 x 45°
0.25
GAGE PLANE
0.36
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
0.19
0.10
OPTION A - BEVEL EDGE
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08Arev14
F) FAIRCHILD SEMICONDUCTOR.
Figure 26. 8-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, .150-Inch Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package draw ings:
http://www.fairchildsemi.com/packaging/ .
? 2011 Fairchild Semiconductor Corporation
FL7701 ? Rev. 1.0.4
12
www.fairchildsemi.com
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